1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, a CMOS imager capable of detecting both visible light and near infrared (IR), and an associated fabrication process.
2. Description of the Related Art
FIG. 1 depicts a complementary metal oxide semiconductor (CMOS) imager with a “buried” or “pinned” photodiode and a four-transistor (4T) active pixel sensor (APS) (prior art). Conventionally, the image cell, circuit includes four transistors and one photodiode. The pixel operation is divided into three main stages: reset, exposure, and reading.
(1) The reset stage: by turning on the reset and transfer (Tx) transistors, the photodiode capacitance is charged to a reset voltage. As for the case of the p+np buried photodiode shown in FIG. 1, the buried cathode (n) is totally depleted and set to the pinned voltage (Vpin).
(2) The exposure stage: with the absorption of light by the photodiode, electron and hole pairs are generated. The holes fill the depleted acceptor sites in the p-region, and the electrons fill the depleted donor sites in the n-region. The potential of the photodiode cathode decreases as the photoelectrons fills up at the donor sites.
(3) The reading stage: the pixel value, is read out by a correlated double sampling (CDS) circuit. First, the select transistor and the reset transistor are turned on, the floating diffusion (FD) is set to high, and the output is set to the reference level. Then, the transfer transistor (Tx) is turned, on, the accumulated photo-electrons in the photodiode are transferred to the FD. Photo-charges in FD are converted to the signal voltage by a source follower (SF) and read out as signal voltage level. The signal is constructed, by subtracting the reference voltage level from the signal voltage level (see FIG. 2).
FIG. 2 is a timing diagram associated with of the pixel circuit of FIG. 1 (prior art). The advantage of using a buried photodiode in a CMOS imager sensor is that low dark currents may be obtained. If the charge in the buried n-cathode can be completely depleted during the reset, and the signal electrons in the buried n-cathode can be completely transferred, then zero lag and zero reset noise can be achieved. Several device design parameters optimizations, such as low voltage depleted diode, wide transfer transistor, low threshold voltage, and high gate voltage on transfer transistor must be considered to achieve the complete transfer of the signal electrons in the buried n-cathode.
FIG. 3 is a Bayer color filter pattern (prior art). Conventional CMOS and charge-coupled device (CCD) digital image sensors use a standard photodiode or photogate as the photosensing element. In their native state, the photosensing element, captures the light signal as black-and-white. In order to perform color imaging, small color filters are placed on top of each photo sensing element. Usually the red, green, and blue (RGB) color filters are arranged in a Bayer pattern, as shown, which alternately samples red, green, and blue pixels. A required image-processing step for Bayer pattern sensors is interpolation, during which missing data is estimated from neighboring pixel data. Silicon has characteristic photon absorption lengths that vary with the energy of the photons absorbed. For the wavelengths of 450 nanometers (nm), 550 nm, and 650 nm, the absorption lengths are 0.24 microns (μm), 1.13 μm, and 3.17 μm, respectively. This variation provides an opportunity to fabricate stacked diode junctions at depths that are capable of separating photons of various wavelengths, using standard CMOS manufacturing processes. Various technologies have been applied to this idea over the past 30 years and full color imaging is available in the market place.
In modern CMOS imager fabrication, the APS cell has moved from 3 transistors (3T) to a 4T buried photodiode APS. The advantage of using a buried photodiode in a CMOS imager sensor is that low dark currents may be obtained. If the charge in the buried n-cathode can be completely depleted during the reset, and the signal electrons in the buried n-cathode can be completely transferred, then zero lag and zero reset noise can be achieved.
FIG. 4 is a cross-sectional view of a vertically integrated combination infrared (IR) and visible light photodetection device (prior art). There are several advantages to a solid state image sensor with the capability to separately detect information in the visible range and near IR range at the same time, especially for automobile and surveillance applications. Lyu et al. present a vertically integrated photodiode structure where an IR photodiode is fabricated under a visible light photodiode. In order to get good visible light detection, the depth of the top photodiode is in the range of 2 microns. The photodiode for IR detection is, therefore, fabricated deeper than 2 microns.
In the case of Lyu's device, the top photodiode for the visible light detection can be made as a buried structure, so the pixel cell can be a 4T APS. However, the use of a 4T APS is impractical, as the bottom photodiode for the IR detection is so deep that a complete charge transfer is almost impossible. The photo charge is stored in the deep (n doped) cathode during exposure. After exposure, these charges must be transferred a relatively long distance to the top surface. In the case of a 4T APS, the charge must be transferred to the floating diffusion node before it can be read. If the 4T APS is used for the IR detection, the device has a high noise and image lag resulting from incomplete charge transfer. The design could be enabled using a 3T APS, however, such a CMOS imager is widely known to suffer from high circuit noise and high dark current.
It would be advantageous if a combination full (three) color and IR pixel cell could be simply fabricated using a design that promoted complete charge transfer.